Paper Info
Title
Improving I/O performance with a conditional store buffer
Abstract
Microprocessor I/O performance is becoming increas- ingly critical in order to support efficient communication interfaces as modern microprocessors continue to be used in a variety of multiprocesso r configurations . Numerous performance enhancements have been made to improve processor performance by improving the latency and bandwidth to main memory or creating efficient mecha- nisms to hide main memory latency. These include specu- lative out of order instruction execution, lock-up free caches, and improved memory bus designs. Sadly these im- provements are not directly applicable to improved I/O system performance and may even complicate high perfor- mance I/O system design. This paper introduces and ana- lyzes the design of a simple mechanism called the conditional store buffer. The conditional store buffer im- proves I/O write performance by making better use of the system bus to increase effective I/O bandwidth, while greatly reducing synchronization overhead. The cost is a minor increase in hardware complexity.
Year
DOI
Venue
1998
10.1109/MICRO.1998.742778
MICRO
Keywords
Field
DocType
o performance,conditional store buffer,system performance,memory latency,system design,out of order
Computer science,Parallel computing,Microprocessor,Real-time computing,Multiprocessing,Input/output,Memory bus,Memory-mapped I/O,Out-of-order execution,System bus,CAS latency,Embedded system
Conference
ISBN
Citations 
PageRank 
1-58113-016-3
5
0.63
References 
Authors
8
2
Name
Order
Citations
PageRank
Lambert Schaelicke127920.23
Al Davis298654.47