Name
Abstract | ||
|---|---|---|
The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-qua... |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/JSSC.2012.2211696 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Redundancy,Switches,Delay,Accuracy,Capacitors,Quantization,Clocks | Comparator,Computer science,Control theory,Chip,Electronic engineering,Effective number of bits,Figure of merit,CMOS,Redundancy (engineering),Successive approximation ADC,Quantization (signal processing) | Journal |
Volume | Issue | ISSN |
47 | 11 | 0018-9200 |
Citations | PageRank | References |
14 | 0.93 | 13 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jon Guerber | 1 | 29 | 3.83 |
| Hariprasath Venkatram | 2 | 36 | 6.72 |
| Manideep Gande | 3 | 36 | 5.20 |
| Allen Waters | 4 | 30 | 5.03 |
| Un-Ku Moon | 5 | 836 | 140.98 |