Paper Info
Title
BIST TPG for faults in system backplanes
Abstract
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems change frequently, at the system level, the proposed methodology employs a simple test schedule which can be easily changed whenever the system configuration is changed. Since the boards used in such systems are designed for use in a wide variety of systems, the proposed methodology defines the test objectives to be achieved by a board's BIST circuit in terms of the board's edge pin connections, independent of the configurations of the systems in which the board may be used. It is shown that the combination of the proposed test schedule and the availability, on each board in the system, of any BIST circuit that satisfies the proposed test objectives, guarantees safe testing of faults in backplanes. A programmable test architecture and an algorithm to program the architecture to obtain BIST that satisfies the test objectives is also presented. Finally, the applicability and effectiveness of the methodology is demonstrated via its application to multiple configurations of an example system that uses a VME backplane.
Year
DOI
Venue
1997
10.1145/266388.266516
ICCAD
Keywords
Field
DocType
built-in self test,bist methodology,bist circuit,system backplanes,vme backplane,programmable test architecture,edge pin connections,system configuration,proposed methodology,test objective,proposed test schedule,example system,simple test schedule,bist functionality,built-in self-test,bist tpg,proposed test objective,satisfiability
VMEbus,Architecture,Backplane,Computer science,System configuration,Automatic testing,Real-time computing,Electronic engineering,Embedded system,Built-in self-test,System level
Conference
ISBN
Citations 
PageRank 
0-8186-8200-0
1
0.46
References 
Authors
20
2
Name
Order
Citations
PageRank
Chen-Huan Chiang1537.33
Sandeep K. Gupta21980229.01