Paper Info
Title
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture
Abstract
Reconfigurable processor architectures (RAs) have been proving as an effective way to couple significant performance improvements with severe energy constraints, such as those imposed by modern portable real-time applications. XiRisc is a VLIW RISC processor architecture featuring a reconfigurable dataflow-oriented functional unit, the so-called PiCoGA, allowing run-time dynamic extension of the instruction set. In this paper, we propose a LISA-based Instruction Set Simulator (ISS) for the reconfigurable processor, retargetable through a dynamically linked library that emulates instruction set extension. The ISS comprises a SystemC system-level model with embedded bus architecture and memory hierarchy (on-chip and off-chip) to provide a reconfigurable system-on-chip performance evaluator.
Year
DOI
Venue
2005
10.1109/IPDPS.2005.14
IPDPS
Keywords
Field
DocType
reconfigurable processor,instruction set,couple significant performance improvement,dynamically reconfigurable processor architecture,emulates instruction set extension,lisa-based instruction set simulator,reconfigurable processor architecture,run-time dynamic extension,vliw risc processor architecture,cycle-accurate iss,embedded bus architecture,reconfigurable system-on-chip performance evaluator,embedded computing,chip,system on a chip,functional unit,computer architecture,embedded systems,vliw,processor architecture,reduced instruction set computing,instruction sets,system on chip
Dynamic Extension,Computer architecture,Memory hierarchy,Very long instruction word,Instruction set,Computer science,Parallel computing,Instruction set simulator,SystemC,Reduced instruction set computing,Microarchitecture
Conference
ISBN
Citations 
PageRank 
0-7695-2312-9
7
0.56
References 
Authors
21
6
Name
Order
Citations
PageRank
C. Mucci180.95
Fabio Campi222719.26
Antonio Deledda3554.45
A. Fazzi4948.38
M. Ferri570.56
M. Bocchi670.56