Name
Abstract | ||
|---|---|---|
Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated by experimental results. A factor of (n/logn) reduction in test power is achieved by the use of a nonlinear double-tree-scan (DTS) structure instead of linear scan chain of length n. Concomitantly, by exploiting the permutation feature of DTS, whereby the same test data can be loaded in multiple ways, we also achieve substantial reductions in the test-data volume. By incorporating the Illinois scan (ILS) within this framework, we minimize not only the test time but also achieve further reductions in test-data volume. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/VTS.2010.5469547 | VTS |
Keywords | Field | DocType |
integrated circuit testing,illinois scan,nonlinear scan architecture,hybrid delay test,double tree scan,test cost,test-data volume,fault coverage,fault diagnosis,nonlinear double-tree-scan structure,dts,hybrid delay testing scheme,correlation,very large scale integration,automatic test pattern generation,software testing,computer science,clustering algorithms | Automatic test pattern generation,Nonlinear system,Fault coverage,Computer science,Permutation,Real-time computing,Electronic engineering,Test data,Cluster analysis,Test compression,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1093-0167 | 978-1-4244-6649-8 | 1 |
PageRank | References | Authors |
0.35 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhen Chen | 1 | 218 | 36.23 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Dong Xiang | 3 | 528 | 48.34 |