Name
Title | ||
|---|---|---|
Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis |
Abstract | ||
|---|---|---|
Statistical Timing Analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.
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Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ASPDAC.2008.4483961 | ASP-DAC |
Keywords | Field | DocType |
full chip analysis,non-gaussian statistical timing model,circuit delay,full chip delay distribution,actual chip design,d2d variation,previous method,new method,within-die parameter variation,wid parameter variation,process parameter variation,statistical timing analysis,logic design,statistical analysis,chip design,random variables,chip scale packaging,distributed computing,integrated circuit design,fpga,circuits,chip,semiconductor device modeling | Logic synthesis,Random variable,Semiconductor device modeling,Computer science,Electronic engineering,Chip,Real-time computing,Gaussian,Integrated circuit design,Electronic circuit,Chip-scale package | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-1922-7 | 4 |
PageRank | References | Authors |
0.62 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Katsumi Homma | 1 | 18 | 5.36 |
| Izumi Nitta | 2 | 5 | 1.02 |
| Toshiyuki Shibuya | 3 | 89 | 11.80 |