Name
Abstract | ||
|---|---|---|
This paper presents results of reliability investigation of power VDMOS FET in a Bipolar/CMOS/DMOS technology, encapsulated in hermetic ceramic package, obtained from high temperature gate stress (HTGS at 150 degreesC 1000h), high temperature reverse bias stress (HTRB at 150 degreesC 1000h) and wafer baking (at 250 degreesC 120h) tests. The behavior of DC parameters such as threshold voltage, maximum of transconductance in linear region, on-resistance in linear region, drain leakage current, gate leakage current and drain-source breakdown voltage, is deduced from BP4145B Semiconductor Parameter Analyzer measurements and analyzed. During the baking, this study focuses on N+ contact resistance and on-resistance stabilities. All these analyses demonstrate the high reliability of these power devices. (C) 2001 Elsevier Science Ltd. All rights reserved. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1016/S0026-2714(01)00204-9 | Microelectronics Reliability |
Field | DocType | Volume |
CMOS,Electronic engineering,Engineering,Transistor | Journal | 41 |
Issue | ISSN | Citations |
9 | 0026-2714 | 1 |
PageRank | References | Authors |
0.48 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Rey-Tauriac | 1 | 2 | 2.65 |
| M. Taurin | 2 | 1 | 1.16 |
| O. Bonnaud | 3 | 13 | 9.82 |