Name
Title | ||
|---|---|---|
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme |
Abstract | ||
|---|---|---|
A 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for Display Port version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and reduce the power consumption. The voltage booster generates 1.904 V from 1.2-V supply with fast voltage generation time and small area consumption. A bandwidth controllable equalizer is proposed to optimize channel loss compensation even if the Nyquist frequency of input data changes. The BER for all input data rates is less than 10-12 for 27-1 PRBS and the measured jitter characteristics indicate that the proposed receiver exceeds the DisplayPort jitter tolerance specification. The recovered 1.35-GHz clock shows the peak-to-peak jitter of 29.9 ps and the rms jitter of 3.215 ps for 5.4-Gb/s input. The energy efficiency of the CDR circuit in the receiver is 19.3 pJ/bit at 5.4 Gb/s. The receiver occupies 0.672 mm2 including decoupling capacitors and the CDR core area is 0.44 mm2. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSI.2012.2206456 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
optimisation,bandwidth controllable equalizer,multi-rate operation,multirate operation scheme,voltage booster,time 29.9 ps,voltage generation time,voltage 1.2 v,jitter,active inductor,channel loss compensation,multirate receiver,energy conservation,bit rate 5.4 gbit/s,bit rate 1.62 gbit/s,ber,jitter characteristics,capacitors,clock and data recovery,bit rate 2.7 gbit/s,wireless channels,peak-to-peak jitter,binary phase detector,optimization,phase detectors,displayport jitter tolerance specification,frequency 1.35 ghz,radio receivers,compensation,equalisers,time 3.215 ps,equalizer,error statistics,nyquist frequency,television displays,energy efficiency,displayport version 1.2,quarter rate phase detection,decoupling capacitor,clock and data recovery circuits,inductors,voltage 1.904 v,cdr circuit,logic gates,bandwidth,detectors | DisplayPort,Nyquist frequency,Electronic engineering,Voltage-controlled oscillator,Bandwidth (signal processing),Decoupling capacitor,Jitter,Phase detector,Detector,Mathematics | Journal |
Volume | Issue | ISSN |
59 | 12 | 1549-8328 |
Citations | PageRank | References |
6 | 0.63 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Won-Young Lee | 1 | 38 | 5.93 |
| Kyu-Dong Hwang | 2 | 17 | 2.67 |
| Lee-Sup Kim | 3 | 707 | 98.58 |