| Quantization-Error-Robust Deep Neural Network for Embedded Accelerators | 0 | 0.34 | 2022 |
| Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks | 0 | 0.34 | 2022 |
| A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture | 0 | 0.34 | 2022 |
| Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks | 1 | 0.36 | 2021 |
| Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices | 0 | 0.34 | 2021 |
| A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators | 0 | 0.34 | 2021 |
| A Pragmatic Approach To On-Device Incremental Learning System With Selective Weight Updates | 0 | 0.34 | 2020 |
| An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices | 3 | 0.38 | 2020 |
| Cremon: Cryptography Embedded On The Convolutional Neural Network Accelerator | 0 | 0.34 | 2020 |
| A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS | 0 | 0.34 | 2019 |
| An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM | 1 | 0.36 | 2019 |
| Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. | 0 | 0.34 | 2019 |
| A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices | 0 | 0.34 | 2019 |
| Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration | 0 | 0.34 | 2019 |
| NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks | 7 | 0.46 | 2019 |
| An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices | 2 | 0.38 | 2019 |
| A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. | 0 | 0.34 | 2018 |
| NID: processing binary convolutional neural network in commodity DRAM | 2 | 0.37 | 2018 |
| A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method | 0 | 0.34 | 2018 |
| TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training | 3 | 0.39 | 2018 |
| A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks. | 4 | 0.42 | 2017 |
| Energy-Efficient Design of Processing Element for Convolutional Neural Network. | 1 | 0.36 | 2017 |
| A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. | 0 | 0.34 | 2017 |
| An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface | 2 | 0.39 | 2017 |
| A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm. | 0 | 0.34 | 2016 |
| A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. | 0 | 0.34 | 2016 |
| Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. | 2 | 0.35 | 2016 |
| Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. | 2 | 0.40 | 2016 |
| A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method | 6 | 0.62 | 2016 |
| DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. | 1 | 0.35 | 2016 |
| Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing | 4 | 0.43 | 2015 |
| An Integrated Time Register And Arithmetic Circuit With Combined Operation For Time-Domain Signal Processing | 0 | 0.34 | 2015 |
| A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS | 3 | 0.48 | 2015 |
| A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface | 1 | 0.36 | 2014 |
| A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS | 2 | 0.43 | 2014 |
| An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO) | 0 | 0.34 | 2014 |
| Timing error masking by exploiting operand value locality in SIMD architecture | 0 | 0.34 | 2014 |
| NUAT: A non-uniform access time memory controller | 34 | 0.76 | 2014 |
| A unified graphics and vision processor with a 0.89 µW/fps pose estimation engine for augmented reality | 7 | 0.59 | 2013 |
| A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process. | 3 | 0.45 | 2013 |
| A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory | 11 | 0.71 | 2013 |
| A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD | 1 | 0.38 | 2013 |
| A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. | 1 | 0.39 | 2012 |
| A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer | 3 | 0.42 | 2012 |
| A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme | 6 | 0.63 | 2012 |
| 1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS | 2 | 0.44 | 2012 |
| PowerField: a transient temperature-to-power technique based on Markov random field theory | 0 | 0.34 | 2012 |
| A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient | 0 | 0.34 | 2012 |
| A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications | 5 | 0.54 | 2011 |
| Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors | 2 | 0.39 | 2011 |
