Name
Abstract | ||
|---|---|---|
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the longer untargeted faults, i.e., the test set has a noise or variation tolerant nature. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults efficiently. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1065579.1065802 | DAC |
Keywords | Field | DocType |
fault list,long path,compact test set,test compaction method,process variation tolerance,ordinary test compaction method,two-pattern test,path delay fault,test set,path delay test compaction,test pattern,fault detection,process variation,automatic test pattern generation,compaction,logic circuit,logic circuits | Stuck-at fault,Automatic test pattern generation,Logic gate,Fault coverage,Computer science,Algorithm,Real-time computing,Electronic engineering,Process variation,Test compression,Fault indicator,Test set | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-058-2 | 8 |
PageRank | References | Authors |
0.56 | 22 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seiji Kajihara | 1 | 989 | 73.60 |
| Masayasu Fukunaga | 2 | 21 | 2.77 |
| Xiaoqing Wen | 3 | 790 | 77.12 |
| Toshiyuki Maeda | 4 | 213 | 25.86 |
| Shuji Hamada | 5 | 123 | 7.13 |
| Yasuo Sato | 6 | 38 | 4.46 |