Name
Abstract | ||
|---|---|---|
This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DATE.2009.5090670 | DATE |
Keywords | Field | DocType |
topological approach,recent advance,analog layout synthesis,layout template,advantageous mean,layout constraint,topological encodings,core issue,circuit hierarchy,constraint compliance,layout-aware analog sizing,integrated circuit layout,microelectronics,simulated annealing,computer science,information systems,chip,bottom up,tree data structures,design flow,b trees,encoding,tree graphs,analog circuits,design automation,genetic algorithms,system on chip,rtl design,shape,search space,ip management | Integrated circuit layout,IP-XACT,Topology,Computer science,Tree (data structure),Theoretical computer science,Sizing,IP address management,Template,Hierarchy,Uml profile | Conference |
ISSN | Citations | PageRank |
1530-1591 | 11 | 0.71 |
References | Authors | |
19 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. Graeb | 1 | 126 | 14.24 |
| F. Balasa | 2 | 45 | 6.36 |
| R. Castro-López | 3 | 79 | 18.20 |
| Y.-W. Chang | 4 | 11 | 0.71 |
| F. V. Fernandez | 5 | 85 | 7.07 |
| P.-H. Lin | 6 | 11 | 1.05 |
| M. Strasser | 7 | 11 | 0.71 |