R. Castro-López - Citegraph

Author Info

Name	Affiliation	Papers
R. CASTRO-LÓPEZ	CSIC, IMSE CNM, E-41080 Seville, Spain	41
Collaborators	Citations	PageRank
82	79	18.20
Referers	Referees	References
174	373	214

Search Limit

100373

Publications (41 rows)

Collaborators (82 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems	3	0.43	2020
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications	0	0.34	2020
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits	1	0.43	2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level	1	0.43	2020
Ready-To-Fabricate Rf Circuit Synthesis Using A Layout- And Variability-Aware Optimization-Based Methodology	0	0.34	2020
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors	0	0.34	2019
Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop	4	0.54	2019
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator	0	0.34	2019
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits	0	0.34	2019
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices	0	0.34	2019
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.	1	0.37	2018
CASE: A reliability simulation tool for analog ICs	3	0.57	2017
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization	1	0.36	2017
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging	3	0.64	2017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.	8	0.63	2017
A Size-Adaptive Time-Step Algorithm For Accurate Simulation Of Aging In Analog Ics	2	0.59	2017
Systematic design of a voltage controlled oscillator using a layout-aware approach	1	0.36	2017
An inductor modeling and optimization toolbox for RF circuit design.	5	0.45	2017
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks	0	0.34	2017
Including a stochastic model of aging in a reliability simulation flow	3	0.48	2017
TARS: A toolbox for statistical reliability modeling of CMOS devices	2	0.61	2017
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling.	4	0.49	2017
High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.	1	0.39	2016
Reliability simulation for analog ICs: Goals, solutions, and challenges.	6	1.21	2016
Accurate synthesis of integrated RF passive components using surrogate models	0	0.34	2016
Frequency-dependent parameterized macromodeling of integrated inductors	0	0.34	2016
SIDe-O: A toolbox for surrogate inductor design and optimization	0	0.34	2016
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.	0	0.34	2016
Design space exploration using hierarchical composition of performance models	1	0.36	2015
Physical vs. surrogate models of passive RF devices	0	0.34	2015
Layout-aware Pareto fronts of electronic circuits.	3	0.40	2011
A memetic approach to the automatic design of high-performance analog integrated circuits	6	0.57	2009
AMS/RF-CMOS circuit design for wireless transceivers	0	0.34	2009
Analog layout synthesis: recent advances in topological approaches	11	0.71	2009
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK	5	0.56	2008
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems	0	0.34	2006
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey	0	0.34	2003
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages	0	0.34	2003
Accurate VHDL-based simulation of Sigma-Delta modulators	0	0.34	2003
Retargeting of mixed-signal blocks for SoCs	1	0.37	2001
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design	3	0.48	1999