Name
Abstract | ||
|---|---|---|
A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 4∼65 MHz (×16) and a timing resolution of 9° (40 stages). |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietfec/e89-a.2.385 | IEICE Transactions |
Keywords | Field | DocType |
novel false lock detection,wide frequency operation,digital camera system,wide frequency range,false lock,duty cycle,analog front-end lsis,wide frequency range delay-locked,timing resolution,fine timing resolution,high frequency,delay lock loop,frequency range | Duty cycle,Lock (computer science),Non-blocking algorithm,Delay-locked loop,Real-time computing,Theoretical computer science,Digital camera,Computer hardware,Mathematics | Journal |
Volume | Issue | ISSN |
E89-A | 2 | 0916-8508 |
Citations | PageRank | References |
2 | 0.47 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yasutoshi Aibara | 1 | 2 | 1.14 |
| Eiki Imaizumi | 2 | 4 | 1.36 |
| Hiroaki Takagishi | 3 | 2 | 0.47 |
| Tatsuji Matsuura | 4 | 27 | 8.16 |