Name
Abstract | ||
|---|---|---|
In this paper, a cost efficient test methodology to screen chips that have resistive open defects under the presence of process variation is proposed. The proposed test methodology is based on small delay defect testing. The entire test session is divided into several subsessions. In each subsession, test patterns are applied with a different frequency of test clock, all of which are faster than the rated clock. Unlike others, different test patterns are generated and applied in each subsession to reduce test application time. A simple three step screening method is also proposed. The first step identifies scan outputs that can fail only if there are defects under the possible worst case process variation. In the second step, we assume that a chip failed due to a defect if the number of faulty scan outputs in a test pattern is much larger than that of faulty scan outputs of a typical defect free chip. Finally, the third step screens defective chips by comparing the number of fail patterns. Among 10 benchmark circuits used for the experiments, the proposed method was able to screen successfully more than 90 % of defective chips for 8 circuits. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/VTS.2011.5783771 | 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS) |
Keywords | Field | DocType |
process variation,logic gates,silicon,chip,automatic test pattern generation,cost efficiency | Test method,Automatic test pattern generation,Logic gate,Computer science,Resistive touchscreen,Chip,Electronic engineering,Process variation,Electronic circuit,Computer hardware,Test compression | Conference |
ISSN | Citations | PageRank |
1093-0167 | 0 | 0.34 |
References | Authors | |
14 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seongmoon Wang | 1 | 605 | 48.50 |