Paper Info
Title
A configurable AES processor for enhanced security
Abstract
We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to 219 different AES block cipher schemes within a reasonable hardware cost. Data can be encrypted not only with secret keys and initial vectors, but also by different block ciphers during the communication. A novel on-the-fly key expansion design is also proposed for 28-, 192-, and 256-bit keys. Our unified hardware can run both the original AES algorithm and the extended AES algorithm. The proposed processor design has been fabricated by a 0.25μm CMOS process, with a silicon area of 6.93mm2 - about 200.5K equivalent gates. Under a 66MHz clock, the throughput rate for both the ECB and CBC operation modes are 844.8Mbps, 704Mbps, and 603.4Mbps for 128-bit, 192-bit, and 256-bit keys, respectively.
Year
DOI
Venue
2005
10.1109/ASPDAC.2005.1466189
ASP-DAC
Keywords
Field
DocType
proposed processor design,cmos process,704 mbits/s,cmos integrated circuits,processor design,microprocessor chips,0.25 micron,844.8 mbits/s,configurable aes processor,original aes algorithm,cbc operation mode,different block cipher,66 mhz,proposed architecture,reasonable hardware cost,256-bit key,extended-security communication,encryption,ecb operation mode,logic design,silicon area,integrated circuit design,extended aes algorithm,enhanced security,si,different aes block cipher,603.4 mbits/s,security of data,aes block cipher schemes,block cipher,yield,opc,dissection,secure communication
Logic synthesis,Throughput (business),Block cipher,Computer science,Electronic engineering,Encryption,CMOS,Cmos process,Real-time computing,Integrated circuit design,Processor design,Embedded system
Conference
Volume
ISSN
ISBN
1
2153-6961
0-7803-8736-8
Citations 
PageRank 
References 
8
0.49
13
Authors
4
Name
Order
Citations
PageRank
Chih-Pin Su11459.63
Chia-Lung Horng2281.46
Chih-Tsun Huang367354.07
Wu, Cheng-Wen41843170.44