Name
Title | ||
|---|---|---|
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder |
Abstract | ||
|---|---|---|
In this paper, we present an implementation of a turbo product codes (TPC) decoder achieved on a novel Reconfigurable Multimedia Accelerator (RMA). The RMA is based on the principle of hierarchical shared memory storage managed through a dedicated local controller favoring high data throughput, while squeezing round-trip memory latencies. The mapping methodology facilitates the characterization of the RMA for a TPC decoder in terms of the communication and computation resources. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-00641-8_30 | ARC |
Keywords | Field | DocType |
mapping methodology,turbo product codes decoder,optimizing memory access latencies,high data throughput,tpc decoder,novel reconfigurable multimedia accelerator,hierarchical shared memory storage,round-trip memory latency,turbo product code,dedicated local controller,computation resource,product code,shared memory,memory latency | Registered memory,Uniform memory access,Computer science,Real-time computing,Memory management,Memory bank,Interleaved memory,Shared memory,Parallel computing,Memory map,Distributed shared memory,Multimedia,Embedded system | Conference |
Volume | ISSN | Citations |
5453 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samar Yazdani | 1 | 3 | 1.81 |
| Thierry Goubier | 2 | 53 | 5.41 |
| Bernard Pottier | 3 | 91 | 19.77 |
| Catherine Dezan | 4 | 61 | 8.24 |