Name
Abstract | ||
|---|---|---|
We present a design technique for providing test access to 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The associated optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700684 | ITC |
Keywords | Field | DocType |
integrated circuit testing,tsv,3d core-based soc,test-access solutions,integer programming,linear programming,integer linear programming,system-on-chip,randomized rounding,three-dimensional soc,tam bitwidth,lp-relaxation,optimization method,3d ic,three dimensional,system on chip,lp relaxation | System on a chip,Computer science,Real-time computing,Electronic engineering,Randomized rounding,Integer programming,Three-dimensional integrated circuit,Linear programming,Linear programming relaxation | Conference |
ISSN | ISBN | Citations |
1089-3539 E-ISBN : 978-1-4244-2403-0 | 978-1-4244-2403-0 | 1 |
PageRank | References | Authors |
0.61 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoxia Wu | 1 | 535 | 38.61 |
| Yibo Chen | 2 | 187 | 15.36 |
| K Chakrabarty | 3 | 8173 | 636.14 |
| Yuan Xie | 4 | 6430 | 407.00 |