Name
Abstract | ||
|---|---|---|
This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an OpenRISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEU faults were injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure simulation-based fault injection with only 2.5% FPGA area overhead |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/SSIRI.2008.47 | SSIRI |
Keywords | Field | DocType |
synthesizable verilog hdl models,pure simulation-based fault injection,synthesizable fault model,verilog hdl,seu fault,fpga-based fault injection,fpga-based fault injection tool,fpga circuit,fpga area overhead,case study,fito tool,dependability analysis,controllability,fault tolerance,hardware description languages,fault model,field programmable gate arrays,observability,dependence analysis,real time | Observability,Computer science,OpenRISC,Microprocessor,Field-programmable gate array,Fault tolerance,Verilog,Fault injection,Hardware description language,Embedded system | Conference |
ISBN | Citations | PageRank |
978-0-7695-3266-0 | 13 | 0.85 |
References | Authors | |
19 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Shokrolah-Shirazi | 1 | 24 | 1.53 |
| Seyed Ghassem Miremadi | 2 | 531 | 50.32 |
| Shokrolah-Shirazi, M. | 3 | 13 | 0.85 |