Title
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture
Abstract
This paper presents a VLSI implementation of an MMSE successive interference cancellation multiuser detector (SIC-MUD) for the downlink of a TD-SCDMA system. Computation in the frequency domain, group-wise interference cancellation, and pre-computation of filter coefficients enable an efficient architecture suitable for mobile handsets. Our implementation in 0.13μm CMOS technology proves that the SIC-MUD is a viable solution for the TD-SCDMA downlink, providing a notable performance gain at a moderate increase in complexity compared to linear equalizers.
Year
DOI
Venue
2012
10.1109/VLSI-SoC.2012.6379046
VLSI and System-on-Chip
Keywords
Field
DocType
3G mobile communication,CMOS integrated circuits,VLSI,code division multiple access,filtering theory,frequency-domain analysis,interference suppression,least mean squares methods,mobile handsets,multiuser detection,space division multiple access,time division multiple access,3G downlink,CMOS technology,MMSE successive interference cancellation multiuser detector,SIC-MUD,TD-SCDMA downlink system,VLSI architecture,frequency-domain analysis,groupwise interference cancellation,linear equalizers,mobile handsets,precomputation of filter coefficients,size 0.13 mum
Computer science,Single antenna interference cancellation,Multiuser detection,Electronic engineering,Interference (wave propagation),Time division multiple access,Space-division multiple access,Very-large-scale integration,Filter design,Telecommunications link
Conference
ISSN
ISBN
Citations 
2324-8432
978-1-4673-2656-8
0
PageRank 
References 
Authors
0.34
5
5
Name
Order
Citations
PageRank
Sandro Belfanti100.34
Christian Benkeser2647.86
Karim Badawi321.45
Qiuting Huang4399145.90
A. Burg51426126.54