Name
Abstract | ||
|---|---|---|
In this paper, the design, implementation and simulation of a high-transimpedance gain, ultra low-power dissipation and low-noise CMOS front-end transimpedance amplifier (TIA) is presented. For interfacing with bio-sensor array and analog neuron circuit, an improved capacitive-feedback TIA topology is adopted with active load to obtain a 131 M gain, 1.45 MHz bandwidth, 90.8fA/rt(Hz) input-referred current noise at the sampling frequency, less than 1° phase response at the sampling frequency, and 520 mV peak-to-peak output swing. The proposed circuit dissipates less than 30 μW with 0.8 V supply voltage, and the circuit is implemented in 65 nm CMOS Predictive Technology Model. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/SOCC.2010.5784645 | SoCC |
Keywords | Field | DocType |
cmos analogue integrated circuits,voltage 0.8 v,voltage 520 mv,analog neuron circuit,biosensor array,high-transimpedance gain simulation,integrated circuit modelling,low noise amplifiers,size 65 nm,operational amplifiers,phase response,low-noise cmos front-end transimpedance amplifier,capacitive-feedback tia topology,bandwidth 1.45 mhz,cmos ultra low power dissipation,low-power electronics,sampling frequency,input-referred current noise,cmos predictive technology model,feedback amplifiers,actuators,biosensors,cmos integrated circuits,radio frequency,low power electronics,front end,transimpedance amplifier,sensor array | Computer science,Voltage,Active load,Phase response,Electronic engineering,CMOS,Bandwidth (signal processing),Transimpedance amplifier,Electrical engineering,Operational amplifier,Low-power electronics | Conference |
ISSN | ISBN | Citations |
Pending | 978-1-4244-6682-5 | 0 |
PageRank | References | Authors |
0.34 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiaping Hu | 1 | 2 | 0.74 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| Joseph Ayers | 3 | 33 | 5.17 |