Paper Info
Title
A Hardware Acceleration Unit for MPI Queue Processing
Abstract
With the heavy reliance of modern scientific applications upon the MPI Standard, it has become critical for the implementation of MPI to be as capable and as fast as possible. This has led some of the fastest modern networks to introduce the capability to offload aspects of MPI processing to an embedded processor on the network interface. With this important capability has come significant performance implications. Most notably, the time to process long queues of posted receives or unexpected messages is substantially longer on embedded processors. This paper presents an associative list matching structure to accelerate the processing of moderate length queues in MPI. Simulations are used to compare the performance of an embedded processor augmented with this capability to a baseline implementation. The proposed enhancement significantly reduces latency for moderate length queues while adding virtually no overhead for extremely short queues.
Year
DOI
Venue
2005
10.1109/IPDPS.2005.30
IPDPS
Keywords
Field
DocType
modern scientific application,associative list,fastest modern network,moderate length queue,significant performance implication,mpi standard,important capability,mpi processing,baseline implementation,mpi queue processing,hardware acceleration unit,embedded processor,hardware accelerator,network interface,network interfaces,embedded systems,message passing,acceleration,parallel programming,hardware,software design,bandwidth,prototypes,field programmable gate arrays
Software design,Computer science,Latency (engineering),Parallel computing,Queue,Field-programmable gate array,Bandwidth (signal processing),Hardware acceleration,Message passing,Distributed computing,Network interface
Conference
ISBN
Citations 
PageRank 
0-7695-2312-9
20
1.01
References 
Authors
15
5
Name
Order
Citations
PageRank
Keith D. Underwood184777.39
K. Scott Hemmert257750.62
Arun Rodrigues317215.68
Richard C. Murphy414213.18
Ron Brightwell5106094.72