Paper Info
Title
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating
Abstract
Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0-1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.
Year
DOI
Venue
2010
10.1109/ASPDAC.2010.5419836
ASP-DAC
Keywords
Field
DocType
tree topology,power consumption,clock tree,trees (mathematics),critical pmos transistors,pmos transistor,integer programming,nbti delay degradations,critical-pmos-aware clock tree design,nand-type-matching clock tree,linear programming,integer linear programming,clock gating,clocks,power consumption overhead,different nbti delay degradation,mosfet,zero skew clock gating,clock skew,degradation difference,antiaging zero skew clock gating,degradation,design methodology,soc,data consistency,logic gates,image recognition
Clock signal,Clock gating,Timing failure,Computer science,Clock domain crossing,Electronic engineering,Real-time computing,Synchronous circuit,Clock skew,Digital clock manager,CPU multiplier
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4244-5767-0
5
PageRank 
References 
Authors
0.50
5
4
Name
Order
Citations
PageRank
Shih-Hsu Huang120338.89
Chia-Ming Chang255934.44
Wen-Pin Tu3214.32
Song-Bin Pan481.26