Name
Abstract | ||
|---|---|---|
The computational needs of a program change over time. Sometimes a program exhibits low instruction level parallelism (ILP), while at other times the inherent ILP may be higher; sometimes a program stalls due to a large number of cache misses, while at other times it may exhibit high cache throughput. Asymmetric Multicore Processors (AMP) have been proposed to allow matching the computing needs of a thread to a core where it executes most efficiently. Some of the recent works focus on AMPs consisting of a monolithic large out-of-order (OOO) core and a small in-order (InO) core. Dynamic swapping of threads between these cores is then facilitated to improve energy efficiency of the threads without impacting performance too negatively. Swapping decisions are made at coarse grain instruction granularities to mitigate the impact of migration overhead. This excludes many opportunities for swap at a fine granular level. In this paper we consider a single superscalar OOO core that can morph itself dynamically into an InO core at runtime. In order to determine when to morph from OOO to InO and vice-versa, we rely on certain hardware performance monitors. Using these performance monitors we estimate the energy-delay-squared product (ED2P) for both modes of operation, which is then used to make morphing decisions. The morphing hardware support is simple and is already available in certain Intel processors to facilitate debug. The proposed scheme has low migration overhead, that enables fine-grain morphing to achieve more energy efficient computing by trading a small loss of performance for much greater energy reduction. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCD.2013.6657091 | ICCD |
Keywords | Field | DocType |
asymmetric multicore processor (amp),morphing hardware support,dynamic polymorphing,superscalar core,in-order (ino),superscalar out-of-order core,performance monitoring counter (pmc),intel processors,core morphing,multiprocessing systems,in-order core,out-of-order (ooo),low migration overhead,energy-delay-squared product,hardware performance monitors,energy efficiency,electronic engineering computing | Instruction-level parallelism,Morphing,Cache,Efficient energy use,Computer science,Parallel computing,Real-time computing,Thread (computing),Throughput,Multi-core processor,Embedded system,Debugging | Conference |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sudarshan Srinivasan | 1 | 33 | 5.01 |
| R. Rodrigues | 2 | 111 | 10.56 |
| Arunachalam Annamalai | 3 | 84 | 5.67 |
| Israel Koren | 4 | 1579 | 175.07 |
| Sandip Kundu | 5 | 1103 | 137.18 |