Title
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors
Abstract
Architectural verification is a critical aspect of the microprocessor design cycle. In this paper, we present a design verification environment centered around a biased random instruction generator for simulation-based architectural verification of pipelined microprocessors. The instruction generator uses biases specified by the user to generate instruction sequences for simulation. These biases are not hard-coded and can thus be changed depending on the specific areas in the design and type of design errors being targeted. Correctness checking is achieved using assertion checking and end-of-state comparison with a high-level architectural model. Several architectural-level errors are introduced into a behavioral model of the DLX processor to investigate the processor's response in the presence of design errors. Simulation experiments conducted using the behavioral model show that biased random instruction sequences provide higher coverage of RTL conditional branches and design errors than random instruction sequences or manually-generated test programs. Furthermore, instruction sequences containing a high percentage of read-after-write (RAW) and control dependencies are the most useful.
Year
DOI
Venue
2000
10.1023/A:1008311916502
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Keywords
Field
DocType
architectural verification,biased random instruction generation,correctness checking,coverage metrics,design error coverage,design verification
Computer architecture,Functional verification,Programming language,Computer science,Correctness,Behavioral modeling,Assertion,Real-time computing,Microprocessor design,Architectural model
Journal
Volume
Issue
ISSN
16
1-2
0923-8174
Citations 
PageRank 
References 
6
0.98
13
Authors
3
Name
Order
Citations
PageRank
Ta-chung Chang160.98
Vikram Iyengar2314.34
Elizabeth M. Rudnick386776.37