Name
Abstract | ||
|---|---|---|
This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been used in the past for lower-speed (i.e. 驴12.8 Gbps) applications. However, success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost (off-the-shelf) components are used so that the method can be applied to test scenarios requiring many high-speed channels. Analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method. A Development Platform is also described that facilitates individual module characterization and integration of multiple modules to form customized test systems. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/s10836-009-5124-4 | J. Electronic Testing |
Keywords | Field | DocType |
Multi-GHz test,Serial IO,SiGe,InP,Exclusive-OR,ATE,Jitter | Exclusive or,Computer science,Signal integrity,Communication channel,Real-time computing,Electronic engineering,Scenario testing,Signal synthesis,Circuit performance,Jitter | Journal |
Volume | Issue | ISSN |
26 | 1 | 0923-8174 |
Citations | PageRank | References |
2 | 0.44 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David C. Keezer | 1 | 68 | 17.00 |
| Carl Gray | 2 | 10 | 2.38 |
| Dany Minier | 3 | 28 | 4.32 |
| Patrice Ducharme | 4 | 19 | 2.65 |