Name
Abstract | ||
|---|---|---|
Test access mechanism (TAM) and testing schedule for System-On-Chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper we presents a new method based on genealized rectangle packing, as two-dimensional pacidng. A core cuts into many pieces and utilize the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/APCCAS.2006.342462 | 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS |
Keywords | Field | DocType |
SOC testing, TANL testing scheduling | Design for testing,System on a chip,Computer science,Scheduling (computing),Embedded system,Rectangle packing | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiann-Chyi Rau | 1 | 13 | 6.75 |
| Chien-shiun Chen | 2 | 12 | 1.60 |
| Po-han Wu | 3 | 482 | 31.49 |