Paper Info
Title
Integrated power supply planning and floorplanning
Abstract
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging
Year
DOI
Venue
2001
10.1109/ASPDAC.2001.913372
ASP-DAC
Keywords
Field
DocType
floorplanning algorithm,local power supply wirings,circuit failure,certain circuit block,individual circuit blocks,power supply circuits,graph reduction,local hot spots,integrated planning,circuit layout cad,optimal power supply planning,network flow,optimal power supply planning algorithm,reduced power supply voltage,integrated power supply planning,vlsi,high-performance vlsi design,network graph,integrated circuit layout,power supply consideration,high-quality power supply,power supply planning,insufficient power supply,power bumps,power bump,very large scale integration,system on a chip,routing,cores,intellectual property,vlsi design,voltage,noise reduction,hot spot
Flow network,Integrated circuit layout,System on a chip,Computer science,Circuit Failure,Voltage,Real-time computing,Electronic engineering,Cell relay,Very-large-scale integration,Floorplan
Conference
ISBN
Citations 
PageRank 
0-7803-6633-6
13
1.05
References 
Authors
17
5
Name
Order
Citations
PageRank
I-Min Liu127318.94
Hung-Ming Chen249359.19
Tan-Li Chou318123.80
Adnan Aziz41778149.76
Martin D. F. Wong53525363.70