Paper Info
Title
Fast sequential circuit test generation using high-level and gate-level techniques
Abstract
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.
Year
DOI
Venue
1998
10.1109/DATE.1998.655915
Paris
Keywords
Field
DocType
single stuck-at fault,high fault coverage,gate-level technique,benchmark circuit,combines software testing,gate level,sequential circuit test generation,new approach,high level,high-level vhdl description,test enhancement technique,fault coverage,benchmark testing,registers,system testing,sequential analysis,sequences,software testing,sequential circuits
Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Electronic engineering,Real-time computing,VHDL,Electronic circuit,Test compression,Benchmark (computing),AND gate
Conference
ISBN
Citations 
PageRank 
0-8186-8359-7
30
2.21
References 
Authors
11
6
Name
Order
Citations
PageRank
E. M. Rudnick122016.71
r vietti2342.66
A. Ellis3363.01
F. Corno460255.65
P. Prinetto551655.23
M. Sonza Reorda61099114.76