Name
Abstract | ||
|---|---|---|
The coming ten years promise great changes in silicon technology, with the end of planar bulk CMOS and the rise of interconnect parasitics to true significance. With such shifts in the underlying technology, the simple extrapolation of performance metrics may lead to pronounced prediction errors in design pathfinding. In this work, we utilize newly developed Predictive Technology Models for FinFETs aligned to the 2011 ITRS. Together with predictive interconnect models, we project performance and power landscape for the technology nodes from 20nm to 7nm. We present an overview of models, assess the advantage of FinFET over bulk CMOS devices, benchmark the scaling of critical design metrics, and illustrate major design barriers toward the 7nm node. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2333660.2333666 | ISLPED |
Keywords | Field | DocType |
design pathfinding,finfet predictive technology model,critical design metrics,planar bulk,major design barrier,bulk cmos device,underlying technology,technology node,silicon technology,predictive technology models,performance metrics,integrated circuits,integrated circuit,power,performance,prediction error | Computer science,Electronic engineering,CMOS,Extrapolation,Interconnect parasitics,Critical design,Interconnection,Integrated circuit,Scaling,Benchmarking | Conference |
Citations | PageRank | References |
12 | 1.64 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Saurabh Sinha | 1 | 195 | 21.88 |
| Brian Cline | 2 | 91 | 11.28 |
| Greg Yeric | 3 | 169 | 16.97 |
| Vikas Chandra | 4 | 691 | 59.76 |
| Yu Cao | 5 | 329 | 29.78 |