Name
Abstract | ||
|---|---|---|
Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabilty constraints emerging in VLSI circuits. In this paper a new technique to accurately estimate the transient behavior of large CMOS cell-based circuits in a reasonable amount of time is presented. Gate-level simulations and a consistent modeling methodology are employed to compute the time-domain waveforms for signal voltages, supply currents, power consumption and &Dgr;&Igr; noise on power lines. This can be done for circuit blocks and complete designs by our new tool POWTIM, which adds SPICE-like capabilities to digital design standards. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICCAD.1994.629775 | ICCAD |
Keywords | Field | DocType |
noise estimation,spice-like capability,new tool,complete design,gate-level simulation,digital design standard,power line,power consumption,digital design system,transient power,vlsi circuit,new technique,cmos technology,application specific integrated circuits,voltage,digital design,time domain,very large scale integration,consistency model,semiconductor device modeling | Computer science,Semiconductor device modeling,Voltage,Application-specific integrated circuit,Real-time computing,CMOS,Electric power transmission,Electronic engineering,Electronic circuit,Very-large-scale integration,Electrical engineering,Energy consumption | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-89791-690-5 | 3 |
PageRank | References | Authors |
0.62 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wolfgang T. Eisenmann | 1 | 3 | 0.62 |
| Helmut E. Graeb | 2 | 269 | 36.22 |