Name
Title | ||
|---|---|---|
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control |
Abstract | ||
|---|---|---|
An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2012.2220671 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS memory circuits,SRAM chips,cache storage,optimisation,system-on-chip,voltage control,9T multiVt SRAM,DVFS,ULV SRAM,adaptive supply voltage control,adaptive supply voltage generation,cache memory,custom standard cell library,dynamic PVT compensation,dynamic voltage and frequency scaling,energy 9.94 pJ,energy-efficient SoC,frequency 10 kHz to 94 MHz,low power CMOS technology,multiobjective approach,off-chip performance,power management subsystem,processor cores,propagation delay,size 65 nm,subthreshold RISC processor cores,subthreshold processor,temperature 293 K to 298 K,ultralow voltage SRAM,voltage 1.2 V,voltage 200 mV,voltage 321 mV,voltage 325 mV,CMOS digital integrated circuits,dynamic voltage scaling,low voltage SRAM,subthreshold,ultra-low power | Power management,Propagation delay,Computer science,CPU cache,Voltage,Electronic engineering,Static random-access memory,CMOS,Subthreshold conduction,Frequency scaling | Journal |
Volume | Issue | ISSN |
48 | 1 | 0018-9200 |
Citations | PageRank | References |
6 | 0.60 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sven Lütkemeier | 1 | 44 | 4.09 |
| Thorsten Jungeblut | 2 | 33 | 7.67 |
| Hans Kristian Otnes Berge | 3 | 26 | 2.89 |
| Snorre Aunet | 4 | 119 | 29.60 |
| Mario Porrmann | 5 | 420 | 50.91 |
| U. Rückert | 6 | 755 | 103.61 |