Name
Abstract | ||
|---|---|---|
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. Also, a dynamic reseeding scheme is adopted for further reducing the required hardware overhead. A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage. Experimental results demonstrate the superiority of the proposed LFSR reseeding approach over the already known reseeding techniques. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/764808.764885 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
dynamic reseeding scheme,multiple cell,required hardware overhead,scan-based bist,implementation cost low,multi-phase architecture,required seed,proposed lfsr reseeding approach,different test phase,regular multi-phase,fault coverage,linear feedback shift register | Linear feedback shift register,Fault coverage,State sequence,Computer science,Scan chain,Multi phase,Real-time computing,Electronic engineering,Built-in self-test | Conference |
ISBN | Citations | PageRank |
1-58113-677-3 | 1 | 0.36 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Kalligeros | 1 | 113 | 6.90 |
| X. Kavousianos | 2 | 161 | 12.90 |
| D. Nikolos | 3 | 291 | 31.38 |