Name
Abstract | ||
|---|---|---|
A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1785481.1785570 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
simulated circuit operation,update logic,issue queue design,complete issue logic,circuit delay perspective,out-of-order issue logic,circuit speed,queue update logic,ready signal,oldest ready instruction,issue logic,out of order,instructions per cycle,sorting network,micro architecture | Sorting network,Instructions per cycle,Computer science,Logic optimization,Operand,Electronic engineering,Real-time computing,CMOS,Logic family,Out-of-order execution,Embedded system,Microarchitecture | Conference |
Citations | PageRank | References |
1 | 0.37 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Siddhesh S. Mhambrey | 1 | 1 | 0.37 |
| Lawrence T. Clark | 2 | 155 | 33.27 |
| Satendra Kumar Maurya | 3 | 5 | 1.54 |
| Krzysztof S. Berezowski | 4 | 29 | 3.50 |