| ASAP5: A predictive PDK for the 5 nm node | 0 | 0.34 | 2022 |
| Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node | 0 | 0.34 | 2021 |
| Physically Unclonable Functions Using Foundry SRAM Cells. | 0 | 0.34 | 2019 |
| Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells | 0 | 0.34 | 2019 |
| Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory | 0 | 0.34 | 2019 |
| SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability. | 1 | 0.35 | 2018 |
| Design With Sub-10 Nm Finfet Technologies | 1 | 0.35 | 2017 |
| An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits | 1 | 0.39 | 2016 |
| SRAM-Based Unique Chip Identifier Techniques. | 7 | 0.52 | 2016 |
| Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation | 0 | 0.34 | 2015 |
| Simple And Accurate Single Event Charge Collection Macro Modeling For Circuit Simulation | 1 | 0.63 | 2015 |
| Delay and power tradeoffs for static and dynamic register files | 0 | 0.34 | 2015 |
| Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). | 0 | 0.34 | 2015 |
| Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU | 4 | 0.59 | 2015 |
| Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits | 0 | 0.34 | 2014 |
| Methodology to optimize critical node separation in hardened flip-flops | 2 | 0.60 | 2014 |
| Reducing Transistor Variability for High Performance Low Power Chips | 5 | 0.60 | 2013 |
| SRAM cell optimization for low AVT transistors | 4 | 0.70 | 2013 |
| Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. | 4 | 0.56 | 2013 |
| Low Complexity Out-of-Order Issue Logic Using Static Circuits | 0 | 0.34 | 2013 |
| Energy-efficient architecture and enabling technology for advanced SOCs. | 0 | 0.34 | 2012 |
| Validation of and delay variation in total ionizing dose hardened standard cell libraries. | 1 | 0.39 | 2011 |
| A Specialized Static Content Addressable Memory For Longest Prefix Matching In Internet Protocol Routing | 0 | 0.34 | 2011 |
| Efficient voltage conversion for SRAM low standby power modes | 0 | 0.34 | 2011 |
| Improved Circuits For Microchip Identification Using Sram Mismatch | 8 | 0.94 | 2011 |
| Fast low power translation lookaside buffers using hierarchical NAND match lines | 1 | 0.36 | 2010 |
| Out-of-order issue logic using sorting networks | 1 | 0.37 | 2010 |
| Single event transient mitigation in cache memory using transient error checking circuits | 1 | 0.35 | 2010 |
| In-situ characterization and extraction of SRAM variability | 1 | 0.45 | 2010 |
| Fast and scalable priority encoding using static CMOS | 3 | 0.46 | 2010 |
| Low power fast and dense longest prefix match content addressable memory for IP routers | 1 | 0.37 | 2009 |
| Reducing process variation impact on replica-timed static random access memory sense timing | 0 | 0.34 | 2009 |
| High performance set associative translation lookaside buffers for low power microprocessors | 1 | 0.44 | 2008 |
| Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories | 5 | 0.64 | 2008 |
| Leakage Controlled Read Stable Static Random Access Memories | 1 | 0.38 | 2008 |
| A Low Stanby Power Flip-Flop With Reduced Circuit And Control Complexity | 3 | 1.14 | 2007 |
| LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability | 0 | 0.34 | 2007 |
| Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability | 0 | 0.34 | 2007 |
| Circuit architecture for low-power race-free programmable logic arrays | 2 | 0.39 | 2006 |
| Static Random Access Memory Cells With Intrinsically High Read Stability And Low Standby Power | 2 | 0.40 | 2006 |
| Delay And Area Efficient First-Level Cache Soft Error Detection And Correction | 14 | 1.11 | 2006 |
| Low-power high-performance NAND match line content addressable memories | 7 | 0.67 | 2006 |
| Subthreshold To Above Threshold Level Shifter Design | 14 | 1.85 | 2006 |
| Robust Design of High Fan-In/Out Subthreshold Circuits | 4 | 1.55 | 2005 |
| Managing standby and active mode leakage power in deep sub-micron design | 2 | 0.39 | 2004 |
| Reverse-body bias and supply collapse for low effective standby power | 18 | 3.19 | 2004 |
| Reducing translation lookaside buffer active power | 10 | 0.78 | 2003 |
| Standby power management for a 0.18μm microprocessor | 19 | 5.12 | 2002 |
| VLSI Implementation of Neural Classifiers. | 6 | 0.82 | 1990 |
