Name
Abstract | ||
|---|---|---|
In this paper, a complete non-intrusive test compression solution is proposed for system-on-a-chip (SOC) using embedded FPGA core. The solution achieves low-cost testing by employing not only selective Huffman vertical coding (SHVC) for test stimuli compression, but also MISR-based time compactor for test responses compaction. Moreover, the solution is non-intrusive, since it can tolerate any number of unknown states in output responses such that it does not require modifying the logic of core to eliminate or block the sources ofunknown states. Furthermore, the solution obtains improved diagnostic capability over conventional MISR by combining masking logic with a modified MISR. Experimental results for ISCAS 89 benchmarks as well as a platform FPGA chip have proven the efficiency of the proposed test solution. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/DFTVS.2004.1347866 | DFT |
Keywords | Field | DocType |
masking logic,platform fpga chip,conventional misr,test stimuli compression,test responses compaction,proposed test solution,modified misr,embedded fpga core,complete non-intrusive test compression,non-intrusive test compression,misr-based time compactor,fpga core,data compression,chip,system on a chip,field programmable gate arrays,huffman codes,system on chip | System on a chip,Masking (art),Computer science,Field-programmable gate array,Coding (social sciences),Electronic engineering,Real-time computing,Huffman coding,Data compression,Test compression,Fpga chip | Conference |
ISBN | Citations | PageRank |
0-7695-2241-6 | 3 | 0.40 |
References | Authors | |
13 | 2 | |