Name
Abstract | ||
|---|---|---|
Medium volume VeSFET-based ASICs can fill the gap between high cost microprocessors and low performance FPGAs. Circuits can be customized onto pre-manufactured VeSFET canvases by properly designed interconnects. In this paper, we propose chain canvases, a family of VeSFET canvases for which CMOS-oriented EDA tools can be easily adapted. Footprint area, wire length, via usage, performance and power are compared between chain canvas- and basic canvas-mapped benchmarks. Experimental results show that chain canvas-mapped circuits outperform those mapped to basic canvases. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2451916.2451949 | ISPD |
Keywords | Field | DocType |
designing vesfet-based ics,low performance fpgas,cmos-oriented eda infrastructure,basic canvas-mapped benchmarks,chain canvas-mapped circuit,chain canvas,vesfet-based asics,footprint area,basic canvas,vesfet canvas,eda tool,pre-manufactured vesfet canvas | Computer science,Field-programmable gate array,CMOS,Electronic design automation,Footprint,Electronic circuit,Embedded system | Conference |
Citations | PageRank | References |
1 | 0.39 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiang Qiu | 1 | 23 | 3.28 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| Wojciech Maly | 3 | 1976 | 352.57 |