Paper Info
Title
A bypass scheme for core-based system fault testing
Abstract
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.Fault Detection for Linear Analog Circuits Using Current Injection83590987abs.htm J. Velasco-Medina , Th. Calin, M. NicolaidisReliable Integrated Systems Group, TIMA/INPGA new test technique for linear analog circuits which employs current injection as input test stimulus is described. Our investigations have shown that current transitions resulting from a current injected on internal test points are significantly different for the fault free and faulty circuits. This can be used for fault detection purposes. In fact, the current injection as test input stimulus represents a powerfull alternative to the test approaches based on conventional voltage input stimulus. The new approach allows to improve the testability of various faults, which are difficult to detect or are untestable when using voltage-based test stimulus. In addition the technique has significant advantages for BIST testing purposes. The technique is illustrated by means of a modern opamp circuit and by considering catastrophic and gate-oxide-short (GOS) faults. RAM-Based FPGA's: A Test Approach for the Configurable Logic83590082abs.htm M. Renovell, J. M. PortalLIRMM-UM2J. FiguerasUPC DiagonalY. ZorianLogic Vision Inc.This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.
Year
DOI
Venue
1998
10.1109/DATE.1998.655998
DATE
Keywords
Field
DocType
inpga new test technique,test configurations,internal test point,input test stimulus,test approach,voltage-based test stimulus,test data,current injection,test methodology,core-based system fault testing,bypass scheme,test input stimulus,system testing,shortest path problem,application specific integrated circuits,integrable system,streams,design methodology,electronics industry,patterns,analog circuits,directed graphs,design for test,high level synthesis,fault detection,formal verification
Design for testing,Automatic test pattern generation,Analogue electronics,Computer science,Fault detection and isolation,Field-programmable gate array,Application-specific integrated circuit,Real-time computing,Electronic engineering,Test data,Test compression
Conference
ISBN
Citations 
PageRank 
0-8186-8359-7
0
0.34
References 
Authors
5
2
Name
Order
Citations
PageRank
M. Nourani114915.25
C. Papachristou2565.81