Stability-based algorithms for high-level synthesis of digital ASICs | 2 | 0.50 | 2000 |
A bypass scheme for core-based system fault testing | 0 | 0.34 | 1998 |
A scheme for integrated controller-datapath fault testing | 14 | 1.03 | 1997 |
Structural BIST Insertion Using Behavioral Test Analysis | 3 | 0.39 | 1997 |
False path exclusion in delay analysis of RTL-based datapath-controller designs | 3 | 0.45 | 1996 |
COMET: a hardware-software codesign methodology | 2 | 0.45 | 1996 |
A method for testability analysis and BIST insertion at the RTL | 0 | 0.34 | 1995 |
A neural network based algorithm for the scheduling problem in high-level synthesis | 2 | 0.42 | 1992 |
SYNTEST: an environment for system-level design for test | 30 | 1.90 | 1992 |