Name
Abstract | ||
|---|---|---|
CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1016/j.mejo.2008.11.011 | Microelectronics Journal |
Keywords | Field | DocType |
vertical channel,charge trap flash memory,dominant poly-silicon floating gate,cell structure,novel mosfet structure,better short channel behavior,cmos scaling,arch gate structure,surrounding gate,three-dimensional mosfet,vertical channel double-bit cell,three-dimensional cmos device structure,ulsi era,various device structure,short channel effect,three dimensional | Dynamic random-access memory,Dram,Flash memory,Leakage (electronics),CMOS,Electronic engineering,NAND gate,Engineering,MOSFET,Integrated circuit | Journal |
Volume | Issue | ISSN |
40 | 4-5 | Microelectronics Journal |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Byung-Gook Park | 1 | 7 | 14.38 |
| song jae young | 2 | 0 | 0.68 |
| Jong Pil Kim | 3 | 0 | 1.01 |
| Hoon Jeong | 4 | 7 | 1.29 |
| Jung Hoon Lee | 5 | 263 | 29.59 |
| Seongjae Cho | 6 | 6 | 7.70 |