Paper Info
Title
A shared-FPU architecture for ultra-low power MPSoCs
Abstract
In this work we propose a shared floating point unit (FPU) architecture for ultra low power (ULP) system on chips operating at near threshold voltage (NTV). Since high-performance FP units (FPUs) are large and complex, but their utilization is relatively low, adding one FPU per each core in a ULP multicore is costly and power hungry. In our approach, we share a few FPUs among all the cores in the system. This increases the utilization of FPUs leading to an energy-efficient design. As a part of our approach, we propose two different FPU allocation techniques: optimal and random. Experimental results demonstrate that compared to a traditional private-FPU approach, our technique in a multicore system with 8 processors and 2 shared FPUs can increase the performance/(area*power) by 5x for applications with 10% FP operations and by 2.5x for applications with 25% FP operations.
Year
DOI
Venue
2013
10.1145/2482767.2482772
Conf. Computing Frontiers
Keywords
Field
DocType
ultra low power,ulp multicore,shared fpus,ultra-low power mpsocs,fp operation,traditional private-fpu approach,shared-fpu architecture,high-performance fp unit,multicore system,energy-efficient design,different fpu allocation technique,multicore
Architecture,Floating-point unit,Computer science,Parallel computing,Real-time computing,Multi-core processor,Threshold voltage,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
7
Authors
3
Name
Order
Citations
PageRank
Mohammad Reza Kakoee1878.68
Igor Loi244530.66
Luca Benini3131161188.49