Mohammad Reza Kakoee - Citegraph

Author Info

Name	Affiliation	Papers
MOHAMMAD REZA KAKOEE	Univ Tehran, Tehran, Iran	18
Collaborators	Citations	PageRank
29	87	8.68
Referers	Referees	References
215	475	186

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100475

Publications (18 rows)

Collaborators (29 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A shared-FPU architecture for ultra-low power MPSoCs	0	0.34	2013
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters	8	0.56	2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.	0	0.34	2012
A resilient architecture for low latency communication in shared-L1 processor clusters	6	0.58	2012
Robust Near-Threshold Design With Fine-Grained Performance Tunability.	3	0.43	2012
Row-based FBB: A design-time optimization for post-silicon tunable circuits	0	0.34	2012
A distributed and topology-agnostic approach for on-line NoC testing	27	0.85	2011
A new physical routing approach for robust bundled signaling on NoC links	8	0.54	2010
Automatic synthesis of near-threshold circuits with fine-grained performance tunability	6	0.51	2010
A floorplan-aware interactive tool flow for NoC design and synthesis.	4	0.38	2009
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions	3	0.61	2008
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs	5	0.41	2008
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification	2	0.50	2008
Graph based test case generation for TLM functional verification	1	0.36	2008
A New Approach For Design And Verification Of Transaction Level Models	4	0.40	2007
On-Chip Verification of NoCs Using Assertion Processors	2	0.39	2007
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification	1	0.38	2007
Modified Pseudo LRU Replacement Algorithm	7	0.77	2006

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