Name
Abstract | ||
|---|---|---|
Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architecture for embedded logic analysis that enables real-time lossless compression of debug data. To quantify the gain from using lossless compression in embedded logic analysis, we present a new compression-ratio metric that captures the trade-off between the area and the increase in the observation window. The proposed architecture is particularly suitable for in-field debugging on application boards, which have asynchronous events that inhibit the deterministic replay of debug experiments. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TCAD.2009.2023198 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
elemental semiconductors,logic circuits,network synthesis,silicon,Si,asynchronous events,design errors,embedded logic analysis,in-field debugging,internal circuit nodes,real-time data acquisition,real-time lossless compression,silicon debug,Embedded logic analysis,lossless compression,silicon debug | Journal | 28 |
Issue | ISSN | Citations |
9 | 0278-0070 | 13 |
PageRank | References | Authors |
0.85 | 25 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ehab Anis Daoud | 1 | 23 | 2.05 |
| Nicola Nicolici | 2 | 807 | 59.91 |