Name
Abstract | ||
|---|---|---|
Data prefetching is an effective technique for hiding memory latency. When issued prefetches are inaccurate, performance can degrade. Prior research provided solutions to deal with inaccurate prefetches at the cache and memory levels, but not in the interconnect of a large-scale multiprocessor system. This work introduces application-aware prefetch prioritization techniques to mitigate the negative effects of prefetching in a network-on-chip (NoC) based multicore system. The idea is to rank prefetches from different applications based on their potential utility for the application and propensity to cause interference to other applications. Our evaluation shows that this approach provides significant performance improvements over a baseline that does not distinguish between prefetches from different applications. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2370816.2370886 | PACT |
Keywords | Field | DocType |
application-aware prefetch prioritization technique,memory latency,inaccurate prefetches,large-scale multiprocessor system,effective technique,different application,significant performance improvement,memory level,data prefetching,application-aware prefetch prioritization,on-chip network,multicore system,interconnect,multicore | Cache,Computer science,Parallel computing,Prioritization,Real-time computing,Multiprocessing,Interference (wave propagation),Instruction prefetch,Interconnection,Multi-core processor,CAS latency,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-795X | 978-1-5090-6609-4 | 9 |
PageRank | References | Authors |
0.49 | 10 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nachiappan Chidambaram Nachiappan | 1 | 73 | 4.57 |
| Asit K. Mishra | 2 | 1216 | 46.21 |
| Mahmut T. Kandemir | 3 | 7371 | 568.54 |
| Anand Sivasubramaniam | 4 | 4485 | 291.86 |
| Onur Mutlu | 5 | 9446 | 357.40 |
| Chita R. Das | 6 | 1467 | 80.03 |