Name
Abstract | ||
|---|---|---|
In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed. These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1023/A:1008331029249 | J. Electronic Testing |
Keywords | Field | DocType |
LFSR,low power BIST,low energy consumption,gated clock | Automatic test pattern generation,Computer science,Fault detection and isolation,Filter (signal processing),Real-time computing,Electronic engineering,Combinational logic,Very-large-scale integration,Energy consumption,Low-power electronics,Built-in self-test | Journal |
Volume | Issue | ISSN |
16 | 3 | 1573-0727 |
ISBN | Citations | PageRank |
0-7695-0390-X | 30 | 1.89 |
References | Authors | |
7 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Manich | 1 | 120 | 11.34 |
| A. Gabarró | 2 | 30 | 1.89 |
| michael j lopez | 3 | 30 | 1.89 |
| J. Figueras | 4 | 203 | 16.05 |
| P. Girard | 5 | 478 | 41.91 |
| L. Guiller | 6 | 380 | 24.24 |
| christian landrault | 7 | 30 | 1.89 |
| S. Pravossoudovitch | 8 | 689 | 54.12 |
| João Paulo Teixeira | 9 | 140 | 22.06 |
| marcelino bicho dos santos | 10 | 30 | 1.89 |