Name
Abstract | ||
|---|---|---|
Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. However, the functionality of the functional logic has not been utilized for the test purposes. We propose a low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the functional logic. We show how to analyze the circuit to determine all the free-scan flip-flops and select the best input vector to establish the maximum number of free-scan flip-flops for the scan chain design. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks. In full-scan designs, as many as 89% of the flip-flops are found free-scannable. In the partial-scan designs, we assume that selecting flip-flops for scan to break sequential cycles is used to increase circuit testability. Reduction can be as high as 97% in scan flip-flops needed to break sequential cycles |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/43.720320 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
partial-scan design,significant reduction,full-scan design,free-scan flip-flop,path design,design methodology,circuit testability,functional logic,chain design,actual design,sequential cycle | Journal | 17 |
Issue | ISSN | Citations |
9 | 0278-0070 | 5 |
PageRank | References | Authors |
0.54 | 18 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-chang Lin | 1 | 135 | 10.86 |
| Marek-Sadowska, M. | 2 | 398 | 38.60 |
| M. T.-C. Lee | 3 | 15 | 3.11 |
| Kuang-chien Chen | 4 | 347 | 30.84 |