Title
Design of Fault-Tolerant Solid State Mass Memory
Abstract
This paper presents the flow used for the design of a fault-tolerant Solid State Mass Memory (SSMM) based on Commercial Off The Shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiation on these devices are often complex.In particular, we consider heavy ion and proton induced soft and hard errors in DRAMs devices. In our work, these errors are mitigated at system level rather at device level. In fact the mass memory is based on a suitable ECC code that improves its tolerance with respect to errors induced in DRAMs.The definition of a SSMM architecture is very complex since the design has to take into account the radiation environment and the different system constraints. In this paper we presents the methodology, derived from the Operational Research Theory, used to select the codes and the memory architecture, taking into account the different design constraints.
Year
DOI
Venue
1999
10.1109/DFTVS.1999.802897
DFT
Keywords
Field
DocType
read only memory,fault tolerance,drams,stress,operations research,robustness,error correction,fault tolerant
Dram,Memory scrubbing,Heavy ion,Computer science,Electronic engineering,Real-time computing,Fault tolerance,Commercial off-the-shelf,Solid-state,Memory architecture,System level
Conference
ISBN
Citations 
PageRank 
0-7695-0325-X
8
1.05
References 
Authors
11
5
Name
Order
Citations
PageRank
Gian-carlo Cardarilli111020.75
Stefano Bertazzoni2184.48
Marcello Salmeri318915.48
A. Salsano49013.37
P. Marinucci5394.72