A. Salsano - Citegraph

Author Info

Name	Affiliation	Papers
A. SALSANO	Univ Roma Tor Vergata, Dept Elect Engn, I-00191 Rome, Italy	23
Collaborators	Citations	PageRank
23	90	13.37
Referers	Referees	References
153	214	132

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100214

Publications (23 rows)

Collaborators (23 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Error Detection and Correction in Content Addressable Memories.	4	0.46	2010
Error Correction Codes for SEU and SEFI Tolerant Memory Systems	1	0.38	2009
A Novel Error Detection and Correction Technique for RNS Based FIR Filters	4	0.54	2008
Totally Fault Tolerant RNS Based FIR Filters	9	0.85	2008
Optimization of Self Checking FIR filters by means of Fault Injection Analysis	1	0.38	2007
Concurrent Error Detection in Reed–Solomon Encoders and Decoders	8	0.60	2007
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders	1	0.37	2007
Localization of Faults in Radix-n Signed Digit Adders	4	0.53	2006
Sufficient Conditions to Impose Derivative Constraints on MISO Takagi–Sugeno Fuzzy Logic Systems	2	0.38	2005
On the analysis of Reed Solomon coding for resilience to transient/permanent faults in highly reliable memories	0	0.34	2005
Design of a QCA Memory with Parallel Read/Serial Write	9	1.11	2005
FPGA oriented design of parity sharing RS codecs	0	0.34	2005
A Comparative Evaluation of Designs for Reliable Memory Systems	3	0.54	2005
Design of a Self Checking Reed Solomon Encoder	3	0.49	2005
A self checking Reed Solomon encoder: design and analysis	7	0.84	2005
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities	0	0.34	2004
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems	5	0.85	2004
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker	6	0.53	2003
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology	5	0.55	2001
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines	2	0.40	2001
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture	4	0.68	2000
Development of an evaluation model for the design of fault-tolerant solid state mass memory	4	0.81	2000
Design of Fault-Tolerant Solid State Mass Memory	8	1.05	1999