Name
Title | ||
|---|---|---|
Delay-fault testability preservation of the concurrent decomposition and factorization transformations |
Abstract | ||
|---|---|---|
In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Verification (DV) test set. In addition, we provide new, sufficient conditions for the algebraic resubstitution with complement transformation to preserve RPDF, VNR, and DV testability, that cover a larger class of complementary expressions than was known previously. Experimental results on a set of Berkeley PLA's and MCNC benchmark circuits show that dual extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm, that preserves testability with respect to RPDF, VNR, and DV test sets |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/43.384420 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
dv test set,multiplexor structure,benchmark circuit,dv testability,mcnc benchmark circuit,testability preservation,dual extraction,test set,delay-fault test set,concurrent decomposition,delay-fault testing constraint,factorization transformation,delay-fault testability preservation,logic synthesis,boolean functions,network synthesis,boolean expressions,robustness | Conference | 14 |
Issue | ISSN | Citations |
5 | 0278-0070 | 3 |
PageRank | References | Authors |
0.44 | 13 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. H. El-Maleh | 1 | 13 | 1.76 |
| J. Rajski | 2 | 985 | 63.36 |