Name
Title | ||
|---|---|---|
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits |
Abstract | ||
|---|---|---|
In this paper, we study circuits implemented using high-density arrays composed of vertical slit field effect transistors. This layout style could dramatically increase transistor density and, therefore, reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks, pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCAD.2010.2097191 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
circuit level,super-regular transistor arrangement,metal layer usage,flexible usage,dense cell-level,critical path delay,High-Density Regular Circuits,appropriate cell,Cell Layout-Performance Relationships,transistor density,parallel metal track,available metal layer | Journal | 30 |
Issue | ISSN | Citations |
2 | 0278-0070 | 6 |
PageRank | References | Authors |
0.59 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-wei Lin | 1 | 52 | 5.22 |
| Marek-Sadowska, M. | 2 | 398 | 38.60 |
| Wojciech Maly | 3 | 1976 | 352.57 |