Name
Abstract | ||
|---|---|---|
The existence of sequential redundancy will degrade testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy are converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. In this paper retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits will be enhanced. Experimental results for ISCAS'89 benchmark circuits show effectiveness of this method to optimize the circuits. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/FTCS.1995.466981 | FTCS |
Keywords | Field | DocType |
combinational test generation technique,sequential circuit,benchmark circuit,sequential redundancy,paper retiming,combinational redundancy,sequential redundancy removal,redundancy removal techniques concurrently,combinational circuits,sequential analysis,retiming,redundancy,design for testability,logic circuits,sequential circuits | Design for testing,Testability,Retiming,Logic gate,Sequential logic,Computer science,Parallel computing,Combinational logic,Redundancy (engineering),Electronic circuit | Conference |
ISSN | Citations | PageRank |
0731-3071 | 2 | 0.46 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Seiji Kajihara | 2 | 989 | 73.60 |
| Kozo Kinoshita | 3 | 756 | 118.08 |